1. Field of the Invention
The present invention generally relates to systems that require variable phase bit sampling of data streams and, more particularly, to performance measuring of data bit streams where multiple variable phase sampling devices are required to simultaneously sample the same bit cell at possibly different phases and where synchronization successfully at one phase offset within the bit cell is used at other phase offsets within the bit cell.
2. Description of the Related Art
In recent years, data rates in communications systems have continued to grow at a fast pace and continues to push the physical limits of communications components. Such advances push the need for new performance measuring equipment that can quickly and effectively grade the capabilities of communications systems. Many of these large advances have made older methods obsolete in favor of newer, faster approaches; however, these new approaches require optimized solutions for older, less-considered problems in order to achieve required larger-system performance. Being able to make sampling phase changes without glitching downstream processing is one such problem.
Devices and technologies from SyntheSys Research, Inc. and others require many fast, short measurements of sampled bit data at various phase offsets within a data bit period window. Changing phase offset of bit sampling within a bit period is typically done by using a variable delay mechanism. This element of variable delay for very high performance measuring devices is configured in the clocking path to the sampling device. Variable delays are often placed in the clocking path rather than the data path because of data dependency found in variable delay technology that would distort the data waveform under test. By placing a single-frequency clock signal through the variable delay component, precise and clean delay is achieved. Variable delay technologies that interrupt the clocking signal passing through the variable delay element when delay setting changes are made, will output incomplete or partial clock signals which cause receiving devices that depend on defined bit clock windows or exactly the correct number of clock edges to errantly go into bad states.
Conventional devices that measure performance of data streams utilizing variable delay technology that disrupt the clocking stream are not impacted by the overhead added by the need to resynchronize when delay settings were changed because these devices were limited to making longer-term average bit error rate measurements. Measurements that took many seconds to perform could easily hide resynchronization processes that took a second. However, new measurement methods require that individual measurement periods last many times less than one second, which means that overhead for resynchronization could dominate the time of the measurement if resynchronization was always necessary after each sampling phase change.
There are several commercially available testing systems that characterize and validate the performance of a data signal from a device or communications subsystems using bit error rate measurement methods. These include bit error rate measuring instruments from Agilent Technologies, Anritsu, Advantest and SHF. In each of these systems, non-overlapping techniques are used to create various methods for changing the phase at which bit cells are sampled and performing bit error rate and other measurement techniques. However, these methods require either variable phase setting mechanisms that do not interrupt clocking signals or processing resynchronization at a penalizing rate. It is key to be able to create short and fast measurement intervals utilizing variable phase setting mechanisms that do disrupt clocks as they are cost effective, they implement large delay ranges at very high frequencies and support superior delay resolutions.
Furthermore, no known art exists for mechanisms that allow independently adjusting different phase offsets for two or more tightly synchronized sampling devices such that downstream digital processing elements could simultaneously use the sampling device results while being assured that synchronization had been maintained between the multiple channels during any sampling phase change.
Additionally, no known art exists for mechanisms that allow synchronization taken at one phase offset within the bit cell to be maintained and used after the sampling phase was changed to another phase offset within the bit cell by a variable delay mechanism that would interrupt the clocking signal.
What is needed is a device and method that allows for clocking interruptions that typically occur when making flexible setting of sampling clock phase in high-performance systems to not cause clocking interruptions in downstream processing of post bit-sampled data. Such an invention will enable that synchronization of this post bit-sampled data is not lost from one setting to the next or from one sampling device to the next as in parallel sampling architectures.